Advanced Data Storage Solutions Architect

6 days ago

Bengaluru, Karnataka, India beBeeSenior Full time ₹ 25,00,000 - ₹ 35,00,000

As a Senior Technologist in Asic Development Engineering, you will play a pivotal role in shaping the future of data storage solutions.

About the Role
  • Develop innovative architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes.
  • Collaborate with cross-functional teams to define requirements specs, conceptualize optimal solutions by evaluating architectures, drive implementation, and work closely with layout designers in guiding and reviewing layouts.
  • E nsure timely and high-quality deliverables, provide SOC integration support, and review post-silicon activities from IP characterization to yield improvement and RMA.
  • Provide technical leadership in problem-solving, planning, and mentoring junior and senior engineers.
  • Promote innovation culture and develop efficient processes by adopting state-of-the-art technologies.

Requirements

  • Bachelor's or Master's degree in Electronics, Telecommunication, or Electrical engineering.
  • At least 20 years of experience in IO, including 5 years as a project leader.
  • Proven track record of architecting and leading high-speed interface design solutions from specification through Silicon debug and characterization.
  • Hands-on experience in TX and RX design architectures for high-speed applications such as DDR4, DDR5, LPDDR4, LPDDR5, along with timing budget analysis.
  • Experience in high-speed design architectures such as SERDES, Equalization schemes.
  • Hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant, and Fail-safe IOs.
  • Extensive experience in ESD circuits design, Associated ESD guidelines, and recommendations in different process nodes, IO, and SOC level ESD review and sign-off.
  • Experience in full custom high-speed data path design such as DDR PHY is a plus.
  • Familiarity with tools such as Cadence Virtuoso, Synopsys Custom Compiler, Hspice, Spectre, Finesim, including statistical simulation methodologies.
  • Experience in Mixed-mode simulation and analog-digital co-simulation is an added advantage.
  • Experience in creating EDA models such as Verilog models, Liberty, etc. is an added advantage.
  • In-depth understanding and working knowledge of CMOS process, including FINFET technologies such as 16nm, 7nm, 5nm, and associated DFM issues.

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