Subsystem Timing Specialist

10 hours ago

Allahabad, Uttar Pradesh, India beBeeTiming Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Overview

We are seeking a highly skilled Static Timing Analysis specialist to lead STA activities for complex subsystems.

About the Role:

  • The successful candidate will be responsible for leading STA activities, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • This role involves developing and refining methodologies for STA tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • The ideal candidate will drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentorship and guidance of junior engineers are also key aspects of this role, fostering technical growth and knowledge sharing within subsystem teams.
  • Cross-functional collaboration is essential to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
  • The candidate will present technical solutions and lead discussions with internal teams and customers regarding subsystem-level trade-offs and integration.
Required Skills and Qualifications

Experience and Expertise:

  • Minimum 10 years of experience in Static Timing Analysis for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Prior experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level is preferred.
  • A background in high-speed interfaces or mixed-signal SoC subsystems is beneficial.
Benefits

The successful candidate will have the opportunity to work on cutting-edge projects and collaborate with a talented team of experts. Additionally, they will contribute to the development of innovative methodologies and tools for STA and PNR.

They will also be able to foster their technical skills and knowledge through ongoing training and professional development opportunities.

Why This Role?

This is an exceptional opportunity for a seasoned Static Timing Analysis specialist to take on a leadership role and make a meaningful impact on complex subsystem integration. The ideal candidate will be passionate about driving innovation, collaboration, and technical excellence.

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