Senior Chip Designer

6 hours ago


Bengaluru, Karnataka, India beBeeDesign Full time ₹ 1,04,000 - ₹ 1,30,878

Key Highlights:

  • Experienced Physical Design Engineer required.
  • RTL to GDSII implementation at advanced technology nodes (7nm, 5nm, or below).

Job Description:

We are seeking an accomplished Physical Design Engineer to join our team. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.

The successful candidate will be responsible for the end-to-end physical design flow from RTL to GDSII at advanced technology nodes (7nm, 5nm, or below). This includes:

  1. Floor planning and Partitioning: Optimizing chip area, power, and performance.
  2. Placement and CTS: Optimizing standard cell placement, buffer insertion, and clock tree synthesis.
  3. Routing and Timing Closure: Working on congestion analysis, RC extraction, and static timing analysis (STA).
  4. Power Optimization: Implementing low-power techniques such as clock gating, power gating, and multi-voltage domains.
  5. Physical Verification: Performing DRC, LVS, and Antenna checks using industry-standard tools.
  6. Sign-off Analysis: Working on IR drop, Electro migration (EM), and Signal Integrity (SI) analysis.

Requirements:

Qualifications:

3 to 8 years of experience in Physical Design and Implementation.

Strong knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or Mentor Olympus).

Experience in floor planning, power planning, placement, routing, and timing closure.

Expertise in Static Timing Analysis (STA) using Primetime or Tempus.

Hands-on experience in physical verification tools (Calibre, PVS, or Pegasus).

Good understanding of design constraints, clock tree optimization, IR drop, and power integrity.

Preferred Qualifications:

Experience with 7nm, 5nm, or lower process nodes.

Knowledge of low-power design methodologies.

Familiarity with multi-power domain design (UPF/CPF-based flows).

Why Join Us:

Opportunity to work on cutting-edge semiconductor technology.

Exposure to advanced process nodes and complex designs.

Collaborative and innovative work environment.



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