Principal Chip Layout Specialist

2 days ago

Bengaluru, Karnataka, India beBeePhysicalDesign Full time ₹ 1,80,00,000 - ₹ 2,30,00,000

Our team is seeking a highly motivated and skilled Full Chip Physical Design Engineer to join our SoC implementation team. This individual will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals.

Key Responsibilities:
  • Drive full chip-level physical design flow from RTL to GDSII.
  • Ownership of chip-level floorplanning, partitioning, and integration.
  • Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues.
  • Implement place & route flows including timing closure, IR/EM, and congestion optimization.
  • Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations.
  • Manage static timing analysis (STA) at top level and work closely with timing owners for signoff.
  • Handle power planning and power domain implementation (UPF/CPF-based).
  • Contribute to methodology improvements and automation.
Required Skills and Qualifications:
  • Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
  • 3–6 years of experience in physical design with at least one full chip tapeout.
  • Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre).
  • Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS.
  • Proficiency in scripting languages like Tcl, Perl, Python, or Shell.
  • Familiarity with hierarchical design and ECO flows.
Benefits

This role offers a unique opportunity to grow your skills and contribute to cutting-edge technology projects. You will work closely with experienced engineers to develop innovative solutions and methodologies.

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