DV Team Lead
1 week ago
We are L&T Technology Services, a leading provider of technology services and solutions. We are seeking a highly skilled Senior Design Verification Engineer to join our team. As a key member of our Digital Engineering practice, you will be responsible for delivering high-quality verification environments for our advanced VLSI designs.
About the Job:This is an exciting opportunity to work with a talented team of engineers and contribute to cutting-edge projects. You will develop and maintain verification environments for advanced VLSI designs, implement PCIE protocol coverage models, and collaborate with engineers to bring up and debug xprop, 0-delay gatesims, and power sims.
Responsibilities:- Develop and maintain verification environments for advanced VLSI designs using SV/UVM.
- Implement PCIE protocol coverage models and perform coverage analysis, regression failure triage, and testbench bug fixes.
- Collaborate with engineers to bring up and debug xprop, 0-delay gatesims, and power sims.
- Ensure integration qualification of subunit design/models and VIP in unit DV environment.
- Bachelor's degree in Electrical Engineering or Computer Science.
- At least 5 years of experience in DV engineering for VLSI designs.
- Strong knowledge of SV/UVM and experience with PCIE protocol.
- Excellent problem-solving skills and ability to work collaboratively.
$150,000 - $200,000 per year, depending on experience.
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