Advanced Semiconductor Timing Expert Wanted

3 days ago


Bengaluru, Karnataka, India beBeeTiming Full time ₹ 9,00,000 - ₹ 12,00,000
Senior Timing Analysis Engineer Opportunity

We are seeking a skilled Senior Timing Analysis (STA) Engineer to join our team. The successful candidate will be responsible for driving timing closure of complex SoC and ASIC designs across multiple technology nodes.

The ideal candidate will have strong expertise in timing concepts, constraints development, and signoff methodology. Proficiency in tools like Synopsys Primetime and Cadence Tempus is also required.

Responsibilities:
  • Own and drive timing closure for complex SoC and ASIC designs
  • Perform full-chip and block-level timing analysis using industry-standard tools
  • Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations
  • Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure
Required Skills & Qualifications:
  • 5–10 years of solid hands-on experience in STA and timing closure
  • Strong expertise in timing concepts, constraints development, and signoff methodology
  • Proficient in tools like Synopsys Primetime and Cadence Tempus
  • Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis
  • Good scripting skills (TCL/Perl/Python) to automate and debug flows
Why Join Us?
  • Be part of a high-growth, innovation-driven semiconductor company
  • Work on state-of-the-art technologies with leading global clients
  • Collaborative and empowering work culture


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