
Advanced SOC Design Expert
1 day ago
We are seeking a highly skilled Static Timing Analysis (STA) engineer to join our team. The ideal candidate will have solid experience in timing closure of advanced SoC designs and be proficient in tools like Synopsys Primetime and Cadence Tempus.
This is an excellent opportunity for someone looking to grow their career in a technically challenging environment with access to state-of-the-art technologies and global clients.
Job Description:As a STA engineer, you will be responsible for owning and driving timing closure for complex SoC and ASIC designs across multiple technology nodes. This includes performing full-chip and block-level timing analysis, collaborating with RTL, synthesis, physical design, and verification teams, and developing and maintaining timing constraints.
Required Skills & Experience:- 5-10 years of solid hands-on experience in STA and timing closure
- Strong expertise in timing concepts, constraints development, and signoff methodology
- Proficient in tools like Synopsys Primetime, Cadence Tempus
- Be part of a high-growth, innovation-driven semiconductor company
- Work on state-of-the-art technologies with leading global clients
- Collaborative and empowering work culture
If you're an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you. Please send your resume to apply for this exciting opportunity.
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