Senior RTL Design Expert

3 days ago


Anand, Gujarat, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Title:

Sr RTL Principal Design Engineer

Key Responsibilities:
  • Develop and enhance existing RTL code for PCIe, CXL, IDE, and UALink IP solutions.
  • Add new features to ensure seamless integration with various customer configurations during verification regressions.
Required Skills:
  • 8-16 years of experience in core RTL Design using Verilog.
  • Familiarity with System Verilog and UVM-based environment usage/debugging is essential.
  • Strong understanding of PCIe, CXL, and IDE protocols, along with prior experience in IP development teams, is necessary.
Education and Qualifications:
  • Bachelor's or Master's degree in Electrical, Electronics, or VLSI Engineering.


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