
Physical Designer Leader
2 weeks ago
Senior Physical Design Engineer
Job Description:The successful candidate will be responsible for top-level floor planning, physical design and low power techniques. Key responsibilities include:
- Performing top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Working on advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias in 65nm or lower node designs.
- Providing technical guidance and mentoring to Physical Design Engineers.
- Interface with front-end ASIC teams to resolve issues.
- Closure of DDR2/DDR3/PCIE interfaces through timing optimization.
Key responsibilities also include providing technical guidance and mentoring to Physical Design Engineers, interface with front-end ASIC teams to resolve issues and closure of DDR2/DDR3/PCIE interfaces through timing optimization.
Requirements:The ideal candidate should have a strong background in ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools is required. Additionally, the candidate should possess expertise in scripting languages such as PERL, TCL, strong Physical Verification skill set, Static Timing Analysis in Primetime or Primetime-SI, good written and oral communication skills, ability to clearly document plans and prioritize work based on project needs.
Benefits:This is an excellent opportunity to showcase your expertise in physical design engineering and contribute to the success of Moschip.
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