
Advanced Subsystem Timing Expert
1 week ago
We are seeking a skilled leader to drive our Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems.
- Drive STA and PNR strategies to achieve optimal results across multiple subsystem blocks.
- Develop methodologies tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Responsibilities
- Lead STA and PNR teams in achieving robust timing closure and physical implementation.
- Collaborate with frontend, physical design, and verification teams to integrate complex subsystems.
- Develop and maintain accurate project timelines and milestones.
Requirements
- Minimum 10 years of experience in STA and PNR for complex subsystems within ASIC/SoC design.
- Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus).
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
Skills
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows.
- Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level is preferred.
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