
Principal STA Expert for Advanced Mixed Signal Chips
1 day ago
As a senior ASIC engineer, you will lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip. You will work closely with cross-functional teams to drive timely delivery of complex SoC designs.
- Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
You will be responsible for developing and maintaining methodology and flows related to timing verification and closure. This includes generation of block and full chip timing constraints, analysis of timing reports, and implementation of rapid timing closure.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
- Opportunity for career development and growth.
- Competitive compensation.
- Medical benefits and more.
Work on cutting-edge technologies and take your skills to the next level.
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