Expert ASIC RTL Design Engineer
1 month ago
We are seeking a highly skilled Principal IP Design Engineer to join our team at Mulya Technologies in the US. This is an excellent opportunity for talented engineers who want to work on cutting-edge ASIC and RTL design projects.
About UsMulya Technologies is a well-funded product-based startup founded by Silicon Valley veterans with design centers in Santa Clara, California, and Hyderabad. Our team is passionate about delivering high-quality designs that meet performance, power, and area requirements.
Job DescriptionAs a Principal IP Design Engineer, you will be responsible for creating micro-architecture and detailed design documents, performing RTL coding for complex design blocks, and debugging function and performance simulations. You will also need to understand lint, CDC, synthesis checks, power analysis, and LEC checks, as well as define constraints and track bug reports from beginning to closure.
Key Qualifications- B.E/M. Tech with 8-12 years of experience in ASIC RTL development
- Solid experience with System Verilog
- Experience with Lint, CDC
The estimated annual salary for this position is around $150,000-$200,000 depending on experience and location.
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