Senior ASIC/SoC Design Expert
1 day ago
Wipro is seeking an experienced Senior ASIC/SoC RTL Engineer to lead our IP design team. As a key member of our engineering team, you will be responsible for designing and integrating complex digital circuits using Verilog/System Verilog.
About the RoleThis challenging role involves expertise in SoC subsystem/IP design, integration, and verification. You will work closely with our physical design, verification, and software teams to ensure seamless design execution.
Key Responsibilities- Design and integrate complex digital circuits using Verilog/System Verilog
- Expertise in setting up and using tools like Spyglass Lint/CDC, Synopsys DC, and Verdi/Xcellium
- Understanding of scripting languages like Make flow, Perl, shell, and Python
- Able to help and debug issues for multiple subsystems
- Able to create/review design documents for multiple subsystems
To be successful in this role, you should have:
- 4-15 years of experience in ASIC/SoC design and development
- In-depth knowledge of RTL quality checks (Lint, CDC) and synthesis
- Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) and timing concepts
- Knowledge of one or more interface protocols (PCIe, DDR, Ethernet, I2C, UART, SPI)
As a Wipro employee, you will enjoy a competitive salary package, including a base salary of ₹1,200,000 - ₹1,800,000 per annum, depending on your experience and qualifications. We also offer a range of benefits, including medical insurance, retirement plans, and opportunities for career growth and professional development.
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