Senior ASIC Physical Design Engineer
1 week ago
Overview:
Cisco is seeking a highly skilled Senior ASIC Physical Design Engineer to join our team in Bangalore, India. As a member of this team, you will be responsible for creating next-generation state-of-the-art networking chips in advanced process nodes.
About the Role:
The successful candidate will drive the backend process through the entire RTL 2 GDS implementation flow, including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks, with a focus on performance & die size optimization.
Key Responsibilities:
- Analyze current generation quality and efficiency gaps to identify incremental or evolutionary changes to existing physical design related tools, flows, and methodologies.
- Collaborate with various teams, such as physical design, RTL, DFT, tool/flow owners, and EDA vendors, to improve physical design methodologies.
- Develop a good understanding of different CTS strategies and provide feedback to the implementation team.
- As a member of the physical design team, drive methodologies and best-known methods to streamline and automate physical design work.
- Set up STA, convergence methodology, reviews, and sign-off for multi-mode and multi-corner designs.
- Develop timing ECO implementation strategy convergence and have experience enabling Tweaker/Primetime-based ECO flows.
- Create automation scripts within STA tools for methodology development and possess excellent debugging skills in implementation issues.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Possess good scripting skills (TCL/SHELL/PERL/Python) is a must.
About You:
You are an experienced ASIC engineer with 8+ years of related work experience, having a broad mix of technologies, including:
- All aspects of ASIC physical implementation, including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
- Hierarchical design implementation approach, timing closure, physical convergence.
- Power integrity analysis.
- Experience with large designs (> 100M gates) utilizing state-of-the-art sub 16/14/7/5/3nm technologies.
- Familiarity with various process-related design issues, including design for yield and manufacturability, multi-Vt strategies.
Requirements:
- Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2.
- Synthesis tools: Synopsys DC/FC.
- Formal verification: Synopsys Formality and Cadence LEC.
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