
Senior Chip Design Engineer
2 days ago
This is a highly visible role where you will lead the synthesis, static timing, and design for test efforts for an advanced mixed-signal chip.
You will be part of a talented team responsible for providing integrated solutions into a growth industry.
Key Responsibilities:
- Full chip and block level timing closure ownership throughout the entire project cycle.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Required Skills and Qualifications:
- Bachelor's/Master's/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in static timing analysis tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of process variation effects on timing.
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes.
- Knowledge of low-power techniques including clock gating, power gating, and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
What We Offer:
- Work on leading-edge technologies.
- Opportunity for career development and growth.
- Competitive compensation and benefits package.
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