Design Architect

4 days ago

Shimoga, Karnataka, India beBeePhysical Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Senior ASIC Physical Design Engineer

Job Title: Senior ASIC Physical Design Engineer

Experience: 4+ Years

  • As a senior engineer in physical design, you will be responsible for all aspects of full-chip/block physical design covering floorplanning, placement, budgeting, clock tree planning & analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.
  • You must have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
  • Work closely with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
  • Experienced in design automation.
  • Understanding of timing constraints, SI prevention, and power reduction.
  • Prior experience with Synopsys/Cadence/Mentor place and route tools is required.
  • Must have completed design in 16nm or 7nm.
  • Proficient in Unix/TCL/Perl programming languages.
  • Good communication and presentation skills are required. Requires good interpersonal skills and problem-solving ability.

Minimum Qualifications:

We are looking for candidates with:

  • 4+ years of experience in ASIC physical design.
  • Experience with block implementation, extraction, timing, and/or full-chip designs.
  • Strong communication skills.
  • Strong hands-on TCL/Perl development skills.

Preferred Qualifications:

Candidates with:

  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
  • A track record of taping out complex chips on advanced process nodes.

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