
Senior ASIC Physical Design Engineer
1 week ago
We are seeking a highly skilled and experienced senior physical design engineer to lead our team's efforts in designing and developing complex semiconductor products. This technical role offers opportunities to work on challenging designs, collaborate with cross-functional teams, and drive innovation in the field of ASIC physical design.
Key Responsibilities:- Lead Pre-layout Static Timing Analysis (STA) to assess feasibility and timing constraint validation.
- Develop Chip/Block Level Floorplanning and pin assignment strategies.
- Review top-level/block-level clock specifications for completeness and feasibility.
- Manage physical design tasks, including placement, timing optimization, clock tree synthesis, and routing.
- Perform sign-off tasks, such as RC extraction, static timing analysis, IR drop analysis, and physical verification.
- Presentation and customer interaction in customer meetings.
- Bachelor's degree in Electrical Engineering or equivalent experience.
- 10+ years of experience in ASIC Physical Design or equivalent experience.
- Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes.
- Hands-on experience with EDA tools like ICC2/Innovus.
- Scripting skills in Perl/Tcl/Python.
- Good understanding of ASIC frontend design.
- Experience in both flat and hierarchical layouts.
- Strong problem-solving skills and ability to analyze and resolve physical design issues.
- Experience with power analysis and IR-drop tools, and static timing analysis.
- Expert handling of Verilog HDL based netlists and physical design libraries.
- Team player with good interpersonal and communication skills.
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Physical Design Engineer
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