Digital Design Verification Engineer

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++• Experienced with Verilog, System Verilog, and C or C++• Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader in...

Senior Design verification Engineer Mandatory Skill : PCIE Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Coverage: Achieve functional and code coverage targets through constrained random and directed testing....

Hi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...

ACL Digital is looking for "Senior Design Verification Engineers"Immediate to 30 days Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language...

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using SystemVerilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets...

Job Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage:...

Job Title: Design Verification Engineer Exp Level:4+yrsLocation: Bangalore/HyderabadJob Description:Responsible for ensuring functional correctness of ASIC/SoC designs.Key Task: Develop and execute verification plans for complex digital designs.Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures.Coverage: Achieve...

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong grasp of...

SOC RTL Design VerificationExperience : 4 to 10 YearsLocation : BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...

Job Title: Design Verification Engineer Exp Level:4+yrs Key Task: Develop and execute verification plans for complex digital designs. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Automation: Develop scripts (Python/Perl/TCL)...