Power Optimization Engineer

1 week ago

Hyderabad Secunderabad Telangana, India beBeeOptimization Full time ₹ 15,00,000 - ₹ 20,00,000

The Power Optimization Engineer will play a crucial role in designing and executing power analysis and optimization strategies for new and existing features.

This is an exciting opportunity to work with cross-functional teams, including architects, hardware engineers, and firmware engineers to understand the new features to be verified.

Key Responsibilities:

  • Collaborate with architects, hardware engineers, and firmware engineers to plan and execute power analysis and optimization strategies
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Develop and execute directed and random verification tests
  • Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

  • Experience in power estimation, analysis, and optimization
  • Proficient in using tools such as PTPX/Power Artist
  • Physical design experience with ICC/Innovus, and saif based power optimization is a plus
  • Front end design knowledge data paths understanding, reviewing waveforms etc,. is a plus
  • Knowledge of power management methodologies (including clock gating, power gating, voltage frequency scaling, etc...) is a plus
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Graphics pipeline knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Good working knowledge of SystemC and TLM with some related experience
  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset
  • Desirable assets with prior exposure to video codec system or other multimedia solutions

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