Senior Low Power Design and Verification Engineer

5 days ago

Hyderabad Secunderabad Telangana, India beBeePowerSimulation Full time
Power Simulation Engineer Opportunity

Overview of Job Role :

We are looking for a Power Simulation Engineer to join our team. The ideal candidate will have experience in power domain understanding, HW programming guide sequences, and low power SoC design constructs.

The responsibilities of the role include owning end-to-end DV tasks from coding Test bench and test cases, writing assertions, debugging UPF and RTL, and achieving all coverage goals.

  • Key Responsibilities :
  • Understanding of power domains and hardware programming guide sequences
  • Developing test plans to verify all low power states
  • Owning end-to-end DV tasks from coding Test bench and test cases, writing assertions, debugging UPF and RTL, and achieving all coverage goals
  • Exploring innovative dynamic or static methodologies by engaging with EDA vendors
  • Strong System Verilog/UVM based verification skills Experience with Assertion coverage-based verification methodology
  • Experience in formal / static verification methodologies will be a plus
  • Good understanding of low power design techniques
  • Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
  • Experience with UPF/CPF based power aware verification.
  • Experience with Synopsys NLP (native Low Power) tool.
  • Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus
  • Proficiency in Low-Power standards like UPF/CPF.
  • Working knowledge on UPF based RTL / PGPIN simulations.
  • Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
  • Excellent analytical and problem-solving skills with a focus on power optimization.

Requirements :

To be successful in this role, you will need the following qualifications :

  • 8+ Years of experience in low power simulation and verification
  • Strong knowledge of System Verilog, UVM, and assertion coverage-based verification methodology
  • Experience with Synopsys NLP (native Low Power) tool
  • Good understanding of low power design techniques and low power SoC design constructs
  • Proficiency in UPF/CPF based power aware verification and working knowledge of GLS , PAGLS and scripting languages such as Perl, Python
  • Proficiency in Low-Power standards like UPF/CPF and working knowledge on UPF based RTL / PGPIN simulations
  • Excellent analytical and problem-solving skills with a focus on power optimization

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