Power Systems Architect

2 days ago

Hyderabad Secunderabad Telangana, India beBeeLeader Full time ₹ 1,04,000 - ₹ 1,30,878

Technical Lead

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We are seeking a highly skilled technical leader to join our SOC Power Modeling team. This role involves collaboration with multiple engineering teams, including SoC architecture definition, IP design, integration/physical design, verification, platform architecture, software, and firmware. Your contributions will have a direct impact on the power & performance of our client products.

The Person:

The ideal candidate should have strong SOC design process experience from front end to tapeout. You will lead a team working closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design flow extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Strong verbal and written communication skills are essential for driving technical discussions to successful and actionable outcomes.

Key Responsibilities

  • Team leader for our power modeling group, working with management to define department objectives and growth plans. Make recommendations to improve processes or procedures as appropriate. Implement changes to engineering processes based on new technologies or industry standards. Work with department management on recruiting, hiring, training, and team evaluations .
  • Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level.
  • Lead team with power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met.
  • Work with RTL and physical design teams to scientifically assess and manage tradeoffs with impacts of power management options such as, but not limited to clock and power gating, device type mix and physical implementation options.
  • Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone.
  • Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent.
  • Work with design verification in validating low power design features at SoC and IP level.

Preferred Experience

  • Extensive experience with Synopsys EDA tools, particularly PtPx/Power Artist.
  • Detailed understanding of hardware emulation process, stimulus and EDA flow data extraction.
  • Ability to define data reporting and requirements needs using EDA flows, Tcl and Python based scripting.
  • Ability to work independently and lead a world-wide team.
  • Excellent communication skills, written and verbal skills

Academic Credentials

  • PhD or Master of Science degree in Electrical Engineering, Computer architecture, or Computer Science.
  • 10+ years of experience.

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