Senior Verification Lead
2 weeks ago
Key Qualifications and Skills:
Education and Background: Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.
Experience: 7/10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
Key Responsibilities:
- Experience in development of UVM based verification environments from scratch.
- Architecting and implementing Design Verification infrastructure and executing the full verification cycle.
- Verification of ARM/RISC-V based CPU sub-systems or SoCs.
- Experience with protocols like AMBA, PCIe, DDR, USB, Ethernet.
- Experience with EDA tools and scripting.
Additional Requirements: Experience with revision control systems like Mercurial, Git, or SVN.
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