Senior Design Verification Lead
3 weeks ago
Job Summary: We are seeking a highly motivated and experienced Design Verification Senior Lead to join our team at Tessolve Semiconductors.
Key Responsibilities:
• Lead complex IP verification projects using latest advanced verification languages and methodologies.
• Collaborate with experienced and motivated teams of designers and verification resources to address verification challenges.
• Develop and implement verification strategies for IPs, subsystems, and overall systems.
Technical Requirements:
• Proficient in IP verification using SV/UVM.
• Experienced in SOC verification using C/SV.
• Strong knowledge of VIP integration.
• Familiarity with interconnect protocols (AHB, AXI, APB).
• Experience with SOC interfaces (GPIO, SPI, I2C, UART).
• Knowledge of high-speed serial interfaces (PCIe Gen 3/4, USB, MIPI).
• Experience with memory interfaces (DDR, HBM I/O).
• Strong understanding of coverage closure (code, functional, toggle).
• Proficient in tools like Synopsys VCS or Cadence Incisive.
• Excellent technical documentation skills.
• Good exposure to scripting skills (Perl, Python, Shell, TCL).
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