
Senior SoC Design Test Engineer
1 week ago
We are looking for a skilled Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations.
- Main Responsibilities:
- Develop and execute SoC Scan insertion strategies to ensure integration across various modules.
- Generate and validate ATPG patterns to achieve high fault coverage for SoC designs.
- Perform pattern retargeting and conduct thorough simulations to ensure test reliability and efficiency.
- Debug and resolve test coverage gaps or failures during pattern simulations and silicon testing.
- Collaborate with cross-functional teams to ensure seamless DFT implementation and validation processes.
- Optimize test methodologies to improve yield and reduce test time.
Required Skills and Qualifications:
- Strong hands-on experience in SoC Scan implementation and ATPG pattern generation.
- Proficiency in pattern retargeting and running simulations to ensure high-quality results.
- Familiarity with industry-standard DFT tools like Mentor Tessent, Synopsys TetraMAX, or Cadence Modus.
- Solid understanding of RTL design, verification, and debugging.
- Expertise in scripting languages (e.g., Python, TCL, Perl) for test process automation.
- Problem-solving skills for silicon debug and test failure analysis.
Preferred Qualifications:
- Experience with low-power ATPG techniques and fault diagnostics.
- Knowledge of advanced DFT features such as compression and hierarchical ATPG.
- Exposure to post-silicon validation and production test flows.
Education: Bachelor's/Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
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