Senior Verification Expert
2 days ago
L&T Technology Services seeks a seasoned Senior DV Engineers to lead the development of cutting-edge verification environments.
Key Responsibilities:
- Architect and implement Design Verification infrastructure and execute the full verification cycle.
- Develop UVM based verification environments from scratch.
- Experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies.
- Hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification.
Requirements:
- 8/10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies.
- Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs.
- Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet.
- Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Experience with revision control stems like Mercurial(Hg), Git or SVN.
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Senior Verification Expert
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Senior Verification Expert
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