Senior Silicon Architect

2 weeks ago


Kanpur, Uttar Pradesh, India beBeeDesigner Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Job Title: Lead ASIC Physical Designer

Key Responsibilities:

  • Drive top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Develop low power designs using advanced techniques such as Voltage Islands, Power Gating, and substrate-bias.
  • Provide technical guidance and mentorship to junior engineers.
  • Collaborate with front-end ASIC teams to resolve issues.
  • Deliver Timing closure on DDR2/DDR3/PCIE interfaces.

Requirements:

  • Strong background in ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Extensive experience with Cadence or Synopsys or Magma physical Design Tools.
  • Expertise in scripting languages such as PERL, TCL.
  • Strong Physical Verification skill set.
  • Static Timing Analysis in Primetime or Primetime-SI.

Benefits:

  • Excellent communication skills.
  • Good written and oral communication skills. Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.


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