
Senior DFT Architect
2 weeks ago
Job Title: Senior DFT Architect
Description:
- Develop and implement complex Digital Fault Tolerance (DFT) architectures for System-on-Chip (SoC) designs.
- Prioritize and execute scan, Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), and boundary scan insertion and validation tasks.
- Collaborate with Electronics Design Automation (EDA) vendors to evaluate, deploy, and optimize DFT tool flows.
- Automate repetitive tasks using scripting to enhance efficiency and minimize errors.
- Support test vector generation and validation for Automated Test Equipment (ATE).
- Provide technical guidance and mentorship to junior engineers in the DFT team.
Required Skills and Qualifications:
- Expertise in DFT methodologies, including but not limited to:
- Scan Insertion & Verification
- ATPG (Automatic Test Pattern Generation)
- MBIST (Memory Built-In Self-Test)
- JTAG / Boundary Scan
Benefits:
- Strong problem-solving skills and ability to debug complex test issues.
- Deliver high-quality DFT solutions within tight schedules.
- Experience collaborating with RTL designers, verification engineers, and physical design teams is a plus.
Other Considerations:
- Knowledge of low-power DFT techniques.
- Familiarity with safety-critical standards (ISO 26262, DO-254, etc.).
- Exposure to High-Speed IO testing (SERDES, DDR, etc.).
Candidates must have strong technical skills and experience working with complex digital systems.
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