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17 hours ago
Job Title: Principal Engineer for RTL Design
\- As a Principal Engineer, you will lead the development of Interface Controller IP solutions using Cadence tools.
- This role is based in Bangalore or Noida and involves design and support of the RTL solution.
- Design and Development: Design and develop high-quality RTL code for Interface Controller IP solutions.
- Support and Maintenance: Provide support and maintenance for existing RTL code and ensure it meets customer requirements.
- Education: BE/BTech/ME/MTech in Electrical / Electronics / VLSI with experience as a design and verification engineer.
- Experience: 8-16 years of core RTL Design experience using Verilog is required. System Verilog experience and UVM based environment usage/debugging is also necessary.
- Protocol Experience: PCIe/CXL/IDE experience is needed, with prior experience in implementation of complex protocols.
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