Chief ASIC RTL Digital Design Specialist

1 day ago


Pune, Maharashtra, India beBeeRTLDesigner Full time US$ 90,000 - US$ 1,20,000

Job Overview

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  • Key Responsibilities: Design and implement synthesizable Verilog/System Verilog RTL code for ASIC designs and simulate the performance of these designs using simulation tools.
  • Design Requirements: The ideal candidate must be experienced in lint, CDC, synthesis flow, and static timing flows as well as formal checking. Additionally, experience with high-speed design exceeding 600MHz and P&R aware synthesis, including the usage of tools such as Fusion Compiler, is highly valued.
  • Revision Control: Familiarity with Perforce or similar revision control environments is necessary.
  • Scripting Skills: Knowledge of Perl/Shell scripts is a requirement.
  • Quality Processes: Exposure to quality processes in the context of IP design and verification is an added advantage.
  • Leadership Roles: Prior experience as a Technical Lead for a small team is a significant plus, as it demonstrates the ability to mentor and technically lead a team of designers.
  • Communication and Problem-Solving Skills: Good communication skills, teamwork, problem-solving skills, and high levels of initiative are essential for this role.

 

What We Offer

We provide a collaborative work environment that fosters growth and innovation. Our team is dedicated to delivering high-quality solutions that meet the needs of our clients. If you are passionate about designing and implementing cutting-edge technology, we encourage you to apply for this exciting opportunity.



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