Digital Design Engineer for Critical Blocks
12 hours ago
We are seeking an exceptional digital design engineer to lead our FPGA design efforts and contribute significantly to the logic design of critical FPGA blocks both at the full chip level and within individual modules. As part of our talented engineering team, you will be responsible for employing best-in-class coding styles and methodologies to enhance design quality and accelerate development timelines. You will collaborate closely with the architecture team to define micro-architecture and prepare comprehensive design specifications. Your attention to detail will be crucial in conducting thorough quality checks through linting, CDC, RDC, SDC, and other validation techniques to ensure robust design integrity.
To succeed in this role, you will need a strong background in SoC integration, micro-architecture definition, and experience selecting third-party IP. Proficiency in RTL design and Verilog/System Verilog is essential. Familiarity with ARM processors, AXI/AMBA buses, safety and security protocols, and debug architecture is also advantageous. Knowledge of FPGA design considerations and use cases is a plus. In return, we offer a competitive salary package, including an estimated ₹22,50,000 - ₹27,50,000 per annum.
Key Responsibilities:
• Lead FPGA design efforts and contribute significantly to the logic design of critical FPGA blocks
• Employ best-in-class coding styles and methodologies to enhance design quality and accelerate development timelines
• Collaborate with the architecture team to define micro-architecture and prepare comprehensive design specifications
• Conduct thorough quality checks through linting, CDC, RDC, SDC, and other validation techniques to ensure robust design integrity
• Mentor existing FPGA team members on best practices
• Build and maintain strong relationships with global teams, facilitating effective communication and collaboration
• Take initiative in developing and nurturing talent within the team, fostering a culture of continuous improvement
• Travel occasionally as required for project purposes
Requirements:
• BS/MS in Electronics Engineering, Electrical Engineering, Computer Science, or a related field
• A minimum of 5 years of experience in logic design across various silicon projects
• Proficient in RTL design, with expertise in Verilog and System Verilog
• Strong background in SoC integration, micro-architecture definition, and experience selecting third-party IP
• Familiarity with ARM processors, AXI/AMBA buses, safety and security protocols, and debug architecture is an advantage
• Knowledge of FPGA design considerations and use cases is a plus
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