
Senior Static Timing Analysis Engineer
2 days ago
Job Summary
Achieve exceptional timing closure and physical implementation for complex subsystems, prioritizing power, performance, and area optimization.
Key Responsibilities
- Lead STA and PNR activities for large, multi-interface, or mixed-signal subsystems, ensuring robust design integration.
- Develop tailored methodologies for STA and PNR to address the unique challenges of complex subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor junior engineers, promoting technical growth and knowledge sharing within teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges in complex subsystem integration.
Required Skills and Qualifications
- 10+ years of experience in STA and PNR for complex subsystems, including advanced technology nodes (7nm, below).
- Expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
- Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
- Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
Benefits
- Demonstrated expertise in high-speed interfaces or mixed-signal SoC subsystems.
Others
This is an opportunity to work on complex system projects.
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