
RTL to GDSII Design Expert
3 days ago
Job Opportunity: Experienced RTL to GDSII Design Engineers sought in Bangalore.
The ideal candidate will have a strong background in synthesis, static timing analysis, and physical design processes, with hands-on experience across the complete RTL to GDSII flow. This role requires a deep understanding of EDA tools such as Synopsys Design Compiler (DC) and their application in designing complex ICs.
Responsibilities include:
- Key Responsibilities:
- Develop and maintain DC constraint files for optimal performance and power consumption
- Perform Pre-Timing Synthesis on RTL designs to identify and resolve potential timing issues early in the design cycle
- Execute Pre-Static Timing Analysis (Pre-STA) to ensure that the design meets all timing requirements
- Collaborate with cross-functional teams to achieve design closure and ensure high-quality deliverables
Requirements:
- 5+ years of experience in RTL to GDSII design flow
- Strong background in synthesis, static timing analysis, and physical design processes
- Hands-on expertise in writing DC constraint files for optimal performance and power consumption
- Proven ability to debug and resolve design and timing issues
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