
Senior ASIC Timing Closure Engineer
5 days ago
Join a dynamic team as a Sr. ASIC STA Engineer to drive the synthesis, static timing, and DFT efforts for an advanced mixed-signal chip.
Key Responsibilities
- Own full chip and block level timing closure throughout the entire project cycle (RTL, synthesis, and physical implementation).
- Develop and maintain methodology and flows related to timing verification and closure.
- Generate block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid ECO timing closure.
- Support digital chip integration work and flows.
Requirements
- B.Tech/M.Tech/Ph.D. with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in STA tools and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes.
- Knowledge of timing corners/modes and process variations.
- Knowledge of low-power techniques including clock gating, power gating, and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
- ECO timing flow.
- Strong communication skills are essential as the candidate will interface with various groups.
- Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend-related methodology and tools.
- Ability to solve complex problems and independently drive tasks to completion in a timely manner.
What's in it for you
Work on leading-edge technologies, career development and growth opportunities, competitive compensation, medical benefits, and more.
About Us
Our company offers cutting-edge solutions to its worldwide customers.
Our Culture
We believe in preparing our employees for long-term career development and growth by investing in their continuous learning and professional growth.
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