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2 days ago
Synthesis and Static Timing Analysis
Description:In this pivotal role, you will be at the heart of our Soc design effort, interfacing with various disciplines to drive successful product delivery. As a key member of our development team, you will lead synthesis, static timing, and DFT efforts for advanced mixed-signal chips.
We are a Semiconductor Engineering services startup working on cutting-edge technology nodes while developing state-of-the-art designs in AI/ML, Datacenter, Automotive, and 5G domains. Our engineers collaborate closely with customers to define methodologies and design flows.
This position requires thorough expertise in ASIC design timing closure flow and methodology. A degree in BTech/MTech/PhD with at least 6+ years of hands-on experience in ASIC timing constraints generation and timing closure is necessary. Proficiency in STA tools and methodologies for timing closure, along with a good understanding of OCV, noise, and crosstalk effects on timing, is required.
Responsibilities:- Full chip and block level timing closure ownership throughout the project cycle (RTL, synthesis, and physical implementation).
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
This is an opportunity for career growth and development, working on leading-edge technologies, competitive compensation, medical benefits, and more.
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