System IP Design Verification Expert

3 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,80,00,000 - ₹ 2,40,00,000
Job Title: System IP Design Verification Expert

We are seeking a skilled and detail-oriented engineer to lead the design and verification of our system IPs.

The ideal candidate will have expertise in RISC-V system IP development, including memory management and virtualization. They will thrive in creating robust verification environments using SystemVerilog and UVM, defining and driving verification plans independently.

This position involves working on features that span multiple IPs and devising plans to verify them at IP, subsystem, and fullchip levels. The engineer will also be responsible for owning a large scope with a small focused team, structuring and delivering a configurable IP to SoCs with seamless integration in mind.

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field is required.
  • 7 - 15 Years of Strong experience with System Verilog and UVM-based verification is necessary.
  • Proven ability to drive IP level and subsystem level DV projects is essential.

Benefits:

This role offers opportunities for growth and professional development, working closely with RTL designers, architects, and other engineers. You will gain hands-on experience with complex verification tasks, develop your skills in SystemVerilog and UVM, and contribute to the creation of high-quality system IPs.

Requirements:

  1. Domain understanding of memory management at core/system level.
  2. Experience with SystemVerilog and UVM-based verification.
  3. Ability to drive IP level and subsystem level DV projects.

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