
Subsystem Timing Expert
3 days ago
We are seeking an experienced Static Timing Analysis professional to lead our team in complex subsystems.
- Lead STA and PNR activities for large, multi-block or hierarchical subsystems ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
- Develop and refine methodologies for STA and PNR tailored to the unique challenges of these subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor junior engineers fostering technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Key Responsibilities:
- Ensure timely completion of STA and PNR tasks.
- Collaborate with frontend, physical design, and verification teams to integrate complex subsystems.
- Provide technical guidance to junior engineers.
- Identify and implement process improvements for STA and PNR flows.
Qualifications and Skills:
- 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design including advanced technology nodes (7nm, or below).
- Expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus).
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows.
- Deep understanding of SoC design flows.
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