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5 days ago
We are seeking an experienced Senior DFT Engineer to join our team. The ideal candidate will have a strong background in VLSI design and hardware description languages such as Verilog.
Key Responsibilities:- Develop and execute test insertion flow for scan, MBIST, JTAG
- Estimate and achieve targeted test coverage
- Run RTL and gate-level simulation for all DFT modes
- Develop and debug timing constraints for all DFT modes
- Verify test patterns pre-silicon and post-silicon
- In-depth knowledge of VLSI design and hardware description languages such as Verilog
- Experience with complex block-level and SOC-level DFT execution in advanced finFET technology
- Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent
- Good problem-solving and debug capabilities
- Good knowledge of hardware simulation tools like VCS, Verdi, etc.
- Proficient in scripting languages such as TCL and Perl
- Cross-functional and cross-site teamwork
- Self-driven individual with good communication skills
- Can-do attitude
- Strong team player
- Curious, creative, and good at solving problems
- Execution and results-oriented
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