Senior Digital Full-Test Architect

7 hours ago

Bikaner, Rajasthan, India beBeeDigital Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

**Job Description Summary:**

  • This position involves developing and implementing digital full-test (DFT) architecture with a focus on memory built-in self-test (MBIST) for advanced systems-on-a-chip (SoCs).
  • The candidate will be responsible for integrating MBIST intellectual properties, generating test insertion and verification infrastructure.
  • Other key responsibilities include DFT planning, insertion, simulation, and pattern generation.
  • Furthermore, the individual will perform automatic test pattern generation (ATPG) and MBIST pattern generation and debug failures from silicon bring-up.
  • Collaboration with RTL, physical design, and verification teams throughout the design cycle is essential.
  • Supporting silicon bring-up and yield improvement activities post-silicon are also critical components of this role.

Required Skills and Qualifications:

  • A bachelor's or master's degree in electronics or a related field.
  • A minimum of 7+ years of hands-on experience in DFT with a strong focus on ATPG, scan, and MBIST.
  • Proficiency in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
  • A solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
  • Experience with memory test algorithms, repair analysis, and pattern generation.
  • Familiarity with scripting languages (TCL, Perl, Python) for automation.
  • Strong analytical and problem-solving skills with the ability to work independently.

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