Senior Memory Layout Designer

2 days ago


Amrāvati, Maharashtra, India beBeeMemoryLayoutEngineer Full time ₹ 13,50,000 - ₹ 20,25,000

Job Overview

About the Role
  • We are seeking an experienced memory layout engineer to develop cutting-edge memory compilers layouts and Fast Cache instances layouts for next-generation Cores.
Key Responsibilities
  • Design and implement high-performance, low-power memory layouts that meet stringent area constraints.
  • Analyze and optimize memory performance using advanced EMIR analysis techniques.
  • Collaborate with cross-functional teams to integrate memory designs into complex SoC architectures.
  • Maintain and improve existing memory design flows using Cadence or Synopsys tools.
Requirements
  • Bachelor's degree in Electronic Engineering or equivalent field with a minimum of 5 years of experience in memory layout design.
  • Expertise in CMOS logic design, layout, and transistor behavior is essential.
  • Strong understanding of power, performance, and area trade-offs in CMOS design.
  • Excellent problem-solving skills, ability to analyze complex technical issues and develop innovative solutions.
  • Effective communication and collaboration skills, with experience working in a team environment.
Nice to Have Skills and Experience
  • Familiarity with scripting languages such as Perl.
  • Experience working on Cadence or Synopsys flows and SRAM / memory layouts creation and backend verifications.


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