Senior Mixed Signal Verification Engineer
21 hours ago
The ideal candidate will have the opportunity to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various SoCs.
- Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
- Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
- Quality deliverables through regressions
- Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness
- Reviews, and feedback to design/architecture teams.
To be successful in this role, the candidate should possess expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions. Additionally, the candidate should have excellent problem-solving and debugging skills, as well as strong digital design knowledge and experience with SoC design flow.
- Expertise in System Verilog and UVM methodologies
- Strong digital design knowledge and experience with SoC design flow
- Excellent problem-solving and debugging skills
- Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage.
- Prior experience in working on IPs with mixed signal content will be helpful.
- Prior experience of technical leadership will be an asset.
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