Mixed Signal Verification Engineer
3 weeks ago
Job Title : Mixed-Signal Verification Engineer
Location : Bangalore / Bhopal
Experience Required : 5+ Years
Job Summary :
We are hiring a Mixed-Signal Verification Engineer with 5+ years of hands-on experience in verifying analog/mixed-signal IPs and SoCs.
The role involves developing UVM-based testbenches, creating analog behavioral models, running mixed-signal simulations, and ensuring coverage closure. You'll collaborate with both analog and digital design teams to validate highly integrated and performance-critical IPs.
Key Responsibilities :
- Develop and execute verification plans for mixed-signal designs.
- Build SystemVerilog/UVM testbenches at block and top level.
- Model analog blocks using Verilog-AMS, VHDL-AMS, or wreal.
- Perform mixed-signal simulations using tools like Spectre AMS, Xcelium, or VCS AMS.
- Debug simulation issues across analog and digital domains.
- Write assertions, checkers, scoreboards, and functional coverage models.
- Automate verification flows using scripting languages.
- Collaborate with designers to resolve coverage and functional issues.
Required Skills :
- Strong background in mixed-signal verification methodology.
- Experience in SystemVerilog, UVM, and Real-Number Modeling (RNM).
- Proficiency in analog simulators : Spectre AMS, Xcelium, or similar.
- Hands-on with Verilog-AMS, wreal, and mixed-signal simulation.
- Scripting in Tcl, Python, Perl, or Shell.
- Experience working with IPs like ADCs, DACs, PLLs, SERDES, or LDOs.
Preferred Qualifications :
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or VLSI.
- Understanding of power-aware verification and AMS co-simulation flows.
- Experience in functional coverage and assertion-based verification.
- Familiarity with CDC/RDC tools and low-power verification concepts.
- Strong debugging, communication, and cross-functional collaboration skills.
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