Senior Verification Engineer

4 weeks ago

Bengaluru, Karnataka, India Analog Devices Full time
Job Description

We are seeking a highly skilled Senior Verification Engineer to join our team at Analog Devices. As a key member of our verification team, you will be responsible for leading the verification effort for complex digital SOCs, including end-to-end SOC verification, verification of complex microprocessor designs, and high-speed peripherals.

Key Responsibilities
  • Lead the verification effort for complex digital SOCs, including end-to-end SOC verification, verification of complex microprocessor designs, and high-speed peripherals.
  • Define tasks for team members, coordinate team effort, track, guide, mentor, and provide technical support to team.
  • Work with design and architecture team to define requirements, coordinate for verification deliverables and receivables.
  • Work with Emulation, System FPGA, and Software teams to define post-silicon validation requirements and intercept all post-silicon requirements in pre-silicon verification.
  • Identify, code, and validate end-to-end system use case scenarios.
  • Develop and implement UVM testbench architecture and DV flows, methodologies.
  • Define test plans, tests, and verification methodology for block/subsystem and chip-level verification.
  • Work with other verification team disciplines like emulation, FPGA, and Firmware teams to determine correct functionality.
  • Formal verification of IPs and Subsystems.
  • NOC, Interconnect verification.
  • Performance verification and performance analysis of complex SOCs end-to-end scenarios.
  • System-level use case scenarios definition, coding, and verification.
  • Innovate verification solutions to hit deliverable schedules.
  • Exposure to and learning of state-of-the-art verification techniques such as formal, emulation, portable stimulus, and virtual platforms.
  • Develop verification strategy for a product after going through product requirements and design specifications.
Requirements
  • B.Tech/M.Tech with 12+ years of industry experience in Digital Pre-Silicon verification.
  • Experience in leading IP, Subsystem, or SOC-level verification.
  • Good understanding of SOC/Subsystem design concepts and design architectures.
  • Hands-on experience in developing, updating, and debugging of Verilog, SV-UVM, SOC-level testbenches.
  • Experience in closing the verification of block, subsystem-level verification using industry-standard metrics like code and functional coverage.
  • Expertise on NOC, Bus, and Interconnect Verification. Coverage Analysis and improvements.
  • Test Bench, TB, environment, architect, and implement verification flow and methodology.
  • Power-aware verification with UPF, Power analysis, and Power optimization.
  • Formal verification, define formal verification flow, connectivity, and functional verification using formal tools.
  • Gate-level Simulation with timing annotated.
  • Strong knowledge of test-plan generation, coverage analysis, transaction-level modeling, pseudo, and constrained random techniques with System Verilog.
  • In-depth knowledge of SV-UVM and debugging of testbenches.
  • Assertion and formal knowledge are an advantage.
  • Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica, Neural Network, GPU Cores is a plus.
  • System Verilog, C/C++, System C, TCL/Python/shell-scripting.
  • Experience in analog and mixed-signal verification (ADC/DAC/PLL/Sensors/PHY) is an added advantage.
  • Exceptional interpersonal and communication skills, collaborate, and influence innovative design development/verification methodologies to a wider team spread across the globe.
  • Quick to adopt new technologies with good problem-solving skills.

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