
Advanced Digital Fault Tolerance Architect
3 days ago
The successful candidate will be responsible for developing and implementing advanced digital fault tolerance architecture for complex ASIC/SOC designs.
This involves designing and verifying DFT structures, including scan chains, boundary scan, MBIST, LBIST, and other test-related features.
You will work closely with cross-functional teams to ensure seamless integration of DFT features and collaborate with ATPG tool experts to generate and validate test patterns for stuck-at, transition, and path delay faults.
Fault simulation and coverage analysis are key aspects of this role, requiring you to perform these tasks to optimize test quality.
In addition, you will support silicon bring-up and debug of test-related issues, working with ATE teams to develop test programs and support production testing.
As a senior engineer in this field, you must have experience in DFT engineering and the ability to take on a challenging role while contributing to the success of our organization.
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