
Chief Digital Fault Tolerance Architect
3 days ago
Senior DFT Engineer
Job Description:- Develop and implement digital fault tolerance architecture for integrated circuit designs.
- Design and verify scan chains, boundary scan (JTAG), memory built-in self-test (MBIST), logic built-in self-test (LBIST), and other test structures.
- Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
- Generate and validate test patterns using automatic test pattern generation (ATPG) tools for stuck-at, transition, and path delay faults.
- Perform fault simulation and coverage analysis to optimize test quality.
- Support silicon bring-up and debug of test-related issues.
- Work with automated test equipment (ATE) teams to develop test programs and support production testing.
- 3+ years of experience in digital fault tolerance engineering.
- Strong understanding of digital circuits, microprocessors, and embedded systems.
- Excellent communication and collaboration skills.
- Opportunity to work on cutting-edge digital fault tolerance projects.
- Collaborative and dynamic work environment.
- Professional growth and development opportunities.
Please submit your updated resume for consideration.
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