Senior Graphics Design Engineer

2 weeks ago

Bengaluru, Karnataka, India beBeeGraphics Full time US$ 1,25,000 - US$ 1,75,000
Job Description

You are a passionate and skilled engineer with expertise in modern processor architecture, digital design, and verification. As a team player with excellent communication skills, you have experience collaborating with other engineers located in different sites/timezones.

Key Responsibilities:

  • Physical Design Implementation:
  • Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts.
  • Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design through mock-taepout.
  • Performance Optimization:
  • Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products.
  • Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives.
  • Verification and Timing Closure:
  • Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP.
  • Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements.
  • Collaboration and Communication:
  • Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores.
  • Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further.
  • Documentation and Reporting:
  • Maintain comprehensive design documentation, methodologies, and updates.
  • Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered.
Preferred Experience

Domain Expertise:

  • Experience with working on complex design and optimizing for performance, power, and area.

Technical Proficiency:

  • Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores.

Proficiency with Industry-Leading EDA Tools:

  • Proficiency with Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime.

Design and Verification:

  • Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks.

Scripting and Automation:

  • Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency.

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