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DFT Architectural Specialist

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Cochin, Kerala, India beBeeSpecialist Full time ₹ 10,00,000 - ₹ 30,50,000

**DFT Architectural Specialist**

We are seeking a highly skilled DFT Architectural Specialist to join our team. As a key member of our technical staff, you will be responsible for defining and implementing DFT architectures for SoCs and IPs.

The successful candidate will have strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan, as well as experience with DFT tools such as Synopsys DFT Compiler, TetraMAX, Mentor Tessent, FastScan, and DFTMAX. Proficiency in scripting languages such as TCL, Perl, Python, and Shell is also required.

Additionally, the ideal candidate will have a good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development is highly desirable.

As a DFT Architectural Specialist, you will work closely with RTL designers to insert DFT logic and resolve DRC violations. You will also collaborate with physical design and verification teams to ensure DFT compliance throughout the flow.

**Key Responsibilities:**

  • Define and implement DFT architecture for SoCs and IPs.
  • Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG).
  • Work with RTL designers to insert DFT logic and resolve DRC violations.
  • Generate and validate test patterns using tools such as TetraMAX, FastScan, DFT Advisor, etc.
  • Analyze and improve fault coverage and test time reduction.
  • Support silicon bring-up and post-silicon validation of test features.
  • Debug and resolve DFT-related issues during synthesis, simulation, and verification.

**Required Skills and Qualifications:**

  • 3-10 years of hands-on experience in DFT implementation.
  • Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan.
  • Experience with DFT tools: Synopsys DFT Compiler, TetraMAX, Mentor Tessent, FastScan, DFTMAX, etc.
  • Proficient in scripting languages such as TCL, Perl, Python, and Shell.
  • Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow.
  • Good understanding of timing constraints, STA, and low-power design considerations in DFT.
  • Experience in handling gate-level simulations and testbench development.

**What We Offer:**

A competitive salary and benefits package, as well as opportunities for professional growth and development.