Technical Lead

2 days ago

Hyderabad Secunderabad Telangana, India beBeeDesign Full time ₹ 15,00,000 - ₹ 28,00,000

Job Description:

","
  • Lead the design verification process for high-performance x86-core ISA features.
  • Develop and architect testbenches, test-bench components for cache, x86 ISA features, clock/reset/power features of processors.
  • Create detailed test plans and execute them, ensuring functional coverage.
  • Improve existing testbench setups and implement coding guideline practices.
  • Collaborate with global design verification teams to drive execution of verification plans.
  • Demonstrate innovating as a team through excellent communication and proper documentation techniques.
","

Preferred Experience:

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  • Strong understanding of design and verification life cycles.
  • Hands-on experience with C/C++/SystemVerilog testbench development.
  • Experience with coverage planning, coding, and coverage closure.
  • Knowledge of microprocessor design-for-debug (DFD) logic.
  • Understanding of low power design verification techniques.
","

Key Responsibilities:

","
  • Verification of high-performance cache coherence features.
  • Development of testbenches and test-bench components for cache, x86 ISA features, clock/reset/power features of processors.
  • Creation of detailed test plans and their execution.
  • Improvement of existing testbench setups and implementation of coding guideline practices.
  • Collaboration with global design verification teams to drive execution of verification plans.
","

What We Offer:

","
  • Opportunity to work on cutting-edge technology.
  • Chance to collaborate with experienced professionals.
  • Professional growth and development opportunities.
","

Requirements:

","
  • 8-12 years of ASIC design verification experience.
  • Strong understanding of design and verification life cycles.
  • Hands-on experience with C/C++/SystemVerilog testbench development.
  • Experience with coverage planning, coding, and coverage closure.
  • Knowledge of microprocessor design-for-debug (DFD) logic.
  • Understanding of low power design verification techniques.
"],

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