Principal Timings Engineer

2 days ago

Kozhikode, Kerala, India beBeeStaticTimingAnalysis Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Opportunity

As a seasoned expert in Static Timing Analysis and Place and Route, you will play a crucial role in leading STA and PNR activities for complex subsystems. Your focus will be on ensuring robust timing closure and physical implementation with a strong emphasis on power, performance, and area optimization.

This is a challenging opportunity to develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems. You will drive automation and validation of timing and physical design data across subsystem boundaries, as well as mentor and guide junior engineers to foster technical growth and knowledge sharing within subsystem teams.

Collaboration is key to success in this role, as you will work cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration. Excellent communication skills are essential to present technical solutions and lead discussions with internal teams and customers regarding subsystem-level trade-offs and integration.

Requirements and Qualifications

10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).

  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
  • Background high-speed interfaces, or mixed-signal SoC subsystems
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