Senior Graphics Physical Design Engineer

23 hours ago

Hyderabad Secunderabad Telangana, India beBeeGraphics Full time
Job Overview

We are seeking a highly skilled RTL Physical Design Engineer to join our team and contribute to the development of cutting-edge graphics IP. The ideal candidate will have expertise in transforming complex RTL designs into robust physical layouts, with a strong focus on performance, power, and area optimization.

Responsibilities
  • Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts using industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes.
  • Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products, collaborating with architecture and front-end design teams to align RTL design with physical constraints and objectives.
  • Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP, implementing and verifying design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements.
  • Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores, providing feedback and suggesting improvements to design methodologies and processes to push the technology envelope further.
Requirements
  • Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area, with a proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores.
  • Technical Proficiency: Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like Prime Time, as well as experience with low-power design methodologies and techniques for high-performance graphics IP.
  • Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks, with strong skills in signal integrity analysis, including crosstalk and IR drop evaluations.
  • Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below), with knowledge of process-related challenges and optimization techniques for graphics applications.
  • Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency, with experience developing and maintaining scripts for design rule checks and optimization processes.
Preferred Qualifications
  • Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

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