
Senior Design Engineer
2 weeks ago
We are seeking a seasoned professional to lead the physical design of next-generation processors.
The ideal candidate will have extensive experience in the field, with a strong background in high-performance designs and expertise in automated synthesis and timing-driven place and route.
Key Responsibilities:
- RTL to GDS2 Flow Management
- Physical Implementation of Power Plan, Synthesis, Placement, CTS, Routing, Extraction, Timing Closure (Tile Level, Full Chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR
- PNR Tool Expertise - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
- PPA Improvement Opportunities Identification and Implementation
Preferred Qualifications:
- 16+ Years of Professional Experience in Physical Design, High-Performance Designs
- Automated Synthesis and Timing-Driven Place and Route for RTL Blocks
- Clock Tree Synthesis, Clock and Power Gating Techniques, Scan Stitching, Design Optimization
- Floorplanning, Design Methodology, IP Integration, Logic Equivalence Checks
- Scripting Language Proficiency (Perl, Tcl)
- STA, Full Chip Timing Experience
- Experience with FinFET Dual Patterning Nodes (16/14/10/7/5nm/3nm)
Academic Requirements:
- Bachelor's or Master's Degree in Electronics/Electrical Engineering
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